;buildInfoPackage: chisel3, version: 3.4.3, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit UART_top : 
  module UART_rx : 
    input clock : Clock
    input reset : Reset
    output io : {flip i_serial_data : UInt<1>, o_rx_done : UInt<1>, o_data : UInt<8>}
    
    reg clkCnterReg : UInt<11>, clock with : (reset => (reset, UInt<11>("h00"))) @[UART_rx.scala 25:28]
    reg bitCnterReg : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[UART_rx.scala 26:28]
    wire _outDataReg_WIRE : UInt<1>[8] @[UART_rx.scala 28:35]
    _outDataReg_WIRE[0] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[1] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[2] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[3] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[4] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[5] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[6] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    _outDataReg_WIRE[7] <= UInt<1>("h00") @[UART_rx.scala 28:35]
    reg outDataReg : UInt<1>[8], clock with : (reset => (reset, _outDataReg_WIRE)) @[UART_rx.scala 28:27]
    reg outRxDoneReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[UART_rx.scala 29:29]
    reg stateReg : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[UART_rx.scala 30:25]
    reg serialDataReg_REG : UInt<1>, clock @[UART_rx.scala 33:38]
    serialDataReg_REG <= io.i_serial_data @[UART_rx.scala 33:38]
    reg serialDataReg : UInt<1>, clock @[UART_rx.scala 33:30]
    serialDataReg <= serialDataReg_REG @[UART_rx.scala 33:30]
    node io_o_data_lo_lo = cat(outDataReg[1], outDataReg[0]) @[Cat.scala 30:58]
    node io_o_data_lo_hi = cat(outDataReg[3], outDataReg[2]) @[Cat.scala 30:58]
    node io_o_data_lo = cat(io_o_data_lo_hi, io_o_data_lo_lo) @[Cat.scala 30:58]
    node io_o_data_hi_lo = cat(outDataReg[5], outDataReg[4]) @[Cat.scala 30:58]
    node io_o_data_hi_hi = cat(outDataReg[7], outDataReg[6]) @[Cat.scala 30:58]
    node io_o_data_hi = cat(io_o_data_hi_hi, io_o_data_hi_lo) @[Cat.scala 30:58]
    node _io_o_data_T = cat(io_o_data_hi, io_o_data_lo) @[Cat.scala 30:58]
    io.o_data <= _io_o_data_T @[UART_rx.scala 35:13]
    io.o_rx_done <= outRxDoneReg @[UART_rx.scala 36:16]
    node _T = eq(UInt<2>("h00"), stateReg) @[Conditional.scala 37:30]
    when _T : @[Conditional.scala 40:58]
      outRxDoneReg <= UInt<1>("h00") @[UART_rx.scala 40:20]
      clkCnterReg <= UInt<11>("h00") @[UART_rx.scala 42:19]
      bitCnterReg <= UInt<4>("h00") @[UART_rx.scala 43:19]
      node _T_1 = eq(serialDataReg, UInt<1>("h00")) @[UART_rx.scala 45:27]
      when _T_1 : @[UART_rx.scala 45:40]
        stateReg <= UInt<2>("h01") @[UART_rx.scala 46:18]
        skip @[UART_rx.scala 45:40]
      else : @[UART_rx.scala 47:20]
        stateReg <= UInt<2>("h00") @[UART_rx.scala 48:18]
        skip @[UART_rx.scala 47:20]
      skip @[Conditional.scala 40:58]
    else : @[Conditional.scala 39:67]
      node _T_2 = eq(UInt<2>("h01"), stateReg) @[Conditional.scala 37:30]
      when _T_2 : @[Conditional.scala 39:67]
        node _T_3 = lt(clkCnterReg, UInt<9>("h01b2")) @[UART_rx.scala 52:25]
        when _T_3 : @[UART_rx.scala 52:47]
          node _clkCnterReg_T = add(clkCnterReg, UInt<1>("h01")) @[UART_rx.scala 53:36]
          node _clkCnterReg_T_1 = tail(_clkCnterReg_T, 1) @[UART_rx.scala 53:36]
          clkCnterReg <= _clkCnterReg_T_1 @[UART_rx.scala 53:21]
          stateReg <= UInt<2>("h01") @[UART_rx.scala 54:18]
          skip @[UART_rx.scala 52:47]
        else : @[UART_rx.scala 55:20]
          clkCnterReg <= UInt<11>("h00") @[UART_rx.scala 57:21]
          node _T_4 = eq(serialDataReg, UInt<1>("h00")) @[UART_rx.scala 58:29]
          when _T_4 : @[UART_rx.scala 58:42]
            stateReg <= UInt<2>("h02") @[UART_rx.scala 59:20]
            skip @[UART_rx.scala 58:42]
          else : @[UART_rx.scala 60:22]
            stateReg <= UInt<2>("h00") @[UART_rx.scala 62:20]
            skip @[UART_rx.scala 60:22]
          skip @[UART_rx.scala 55:20]
        skip @[Conditional.scala 39:67]
      else : @[Conditional.scala 39:67]
        node _T_5 = eq(UInt<2>("h02"), stateReg) @[Conditional.scala 37:30]
        when _T_5 : @[Conditional.scala 39:67]
          node _T_6 = lt(clkCnterReg, UInt<10>("h0364")) @[UART_rx.scala 67:25]
          when _T_6 : @[UART_rx.scala 67:41]
            node _clkCnterReg_T_2 = add(clkCnterReg, UInt<1>("h01")) @[UART_rx.scala 68:36]
            node _clkCnterReg_T_3 = tail(_clkCnterReg_T_2, 1) @[UART_rx.scala 68:36]
            clkCnterReg <= _clkCnterReg_T_3 @[UART_rx.scala 68:21]
            skip @[UART_rx.scala 67:41]
          else : @[UART_rx.scala 69:20]
            clkCnterReg <= UInt<11>("h00") @[UART_rx.scala 70:21]
            node _T_7 = bits(bitCnterReg, 2, 0)
            outDataReg[_T_7] <= serialDataReg @[UART_rx.scala 73:33]
            node _T_8 = lt(bitCnterReg, UInt<4>("h08")) @[UART_rx.scala 74:27]
            when _T_8 : @[UART_rx.scala 74:44]
              node _bitCnterReg_T = add(bitCnterReg, UInt<1>("h01")) @[UART_rx.scala 75:38]
              node _bitCnterReg_T_1 = tail(_bitCnterReg_T, 1) @[UART_rx.scala 75:38]
              bitCnterReg <= _bitCnterReg_T_1 @[UART_rx.scala 75:23]
              skip @[UART_rx.scala 74:44]
            else : @[UART_rx.scala 76:22]
              bitCnterReg <= UInt<4>("h00") @[UART_rx.scala 77:23]
              skip @[UART_rx.scala 76:22]
            skip @[UART_rx.scala 69:20]
          node _T_9 = eq(bitCnterReg, UInt<4>("h08")) @[UART_rx.scala 80:25]
          when _T_9 : @[UART_rx.scala 80:44]
            stateReg <= UInt<2>("h03") @[UART_rx.scala 81:18]
            skip @[UART_rx.scala 80:44]
          else : @[UART_rx.scala 82:20]
            stateReg <= UInt<2>("h02") @[UART_rx.scala 83:18]
            skip @[UART_rx.scala 82:20]
          skip @[Conditional.scala 39:67]
        else : @[Conditional.scala 39:67]
          node _T_10 = eq(UInt<2>("h03"), stateReg) @[Conditional.scala 37:30]
          when _T_10 : @[Conditional.scala 39:67]
            node _T_11 = lt(clkCnterReg, UInt<10>("h0364")) @[UART_rx.scala 87:25]
            when _T_11 : @[UART_rx.scala 87:41]
              node _clkCnterReg_T_4 = add(clkCnterReg, UInt<1>("h01")) @[UART_rx.scala 88:36]
              node _clkCnterReg_T_5 = tail(_clkCnterReg_T_4, 1) @[UART_rx.scala 88:36]
              clkCnterReg <= _clkCnterReg_T_5 @[UART_rx.scala 88:21]
              stateReg <= UInt<2>("h03") @[UART_rx.scala 89:18]
              skip @[UART_rx.scala 87:41]
            else : @[UART_rx.scala 90:20]
              clkCnterReg <= UInt<11>("h00") @[UART_rx.scala 91:21]
              outRxDoneReg <= UInt<1>("h01") @[UART_rx.scala 93:22]
              stateReg <= UInt<2>("h00") @[UART_rx.scala 94:18]
              skip @[UART_rx.scala 90:20]
            skip @[Conditional.scala 39:67]
    
  module UART_tx : 
    input clock : Clock
    input reset : Reset
    output io : {flip i_tx_trig : UInt<1>, flip i_data : UInt<8>, o_tx_busy : UInt<1>, o_tx_done : UInt<1>, o_serial_data : UInt<1>}
    
    reg clkCnterReg : UInt<11>, clock with : (reset => (reset, UInt<11>("h00"))) @[UART_tx.scala 27:28]
    reg bitCnterReg : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[UART_tx.scala 28:28]
    reg inDataReg : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[UART_tx.scala 30:26]
    reg outDataReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[UART_tx.scala 31:27]
    reg outTxBusyReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[UART_tx.scala 32:29]
    reg outTxDoneReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[UART_tx.scala 33:29]
    reg stateReg : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[UART_tx.scala 34:25]
    io.o_serial_data <= outDataReg @[UART_tx.scala 36:20]
    io.o_tx_busy <= outTxBusyReg @[UART_tx.scala 37:16]
    io.o_tx_done <= outTxDoneReg @[UART_tx.scala 38:16]
    node _outTxBusyReg_T = neq(stateReg, UInt<2>("h00")) @[UART_tx.scala 39:28]
    outTxBusyReg <= _outTxBusyReg_T @[UART_tx.scala 39:16]
    node _T = eq(UInt<2>("h00"), stateReg) @[Conditional.scala 37:30]
    when _T : @[Conditional.scala 40:58]
      outTxDoneReg <= UInt<1>("h00") @[UART_tx.scala 43:20]
      clkCnterReg <= UInt<11>("h00") @[UART_tx.scala 45:19]
      bitCnterReg <= UInt<4>("h00") @[UART_tx.scala 46:19]
      node _T_1 = eq(io.i_tx_trig, UInt<1>("h01")) @[UART_tx.scala 48:26]
      when _T_1 : @[UART_tx.scala 48:38]
        outDataReg <= UInt<1>("h00") @[UART_tx.scala 49:20]
        inDataReg <= io.i_data @[UART_tx.scala 51:19]
        stateReg <= UInt<2>("h01") @[UART_tx.scala 52:18]
        skip @[UART_tx.scala 48:38]
      else : @[UART_tx.scala 53:20]
        stateReg <= UInt<2>("h00") @[UART_tx.scala 54:18]
        skip @[UART_tx.scala 53:20]
      skip @[Conditional.scala 40:58]
    else : @[Conditional.scala 39:67]
      node _T_2 = eq(UInt<2>("h01"), stateReg) @[Conditional.scala 37:30]
      when _T_2 : @[Conditional.scala 39:67]
        node _T_3 = lt(clkCnterReg, UInt<10>("h0364")) @[UART_tx.scala 58:25]
        when _T_3 : @[UART_tx.scala 58:41]
          node _clkCnterReg_T = add(clkCnterReg, UInt<1>("h01")) @[UART_tx.scala 59:36]
          node _clkCnterReg_T_1 = tail(_clkCnterReg_T, 1) @[UART_tx.scala 59:36]
          clkCnterReg <= _clkCnterReg_T_1 @[UART_tx.scala 59:21]
          stateReg <= UInt<2>("h01") @[UART_tx.scala 60:18]
          skip @[UART_tx.scala 58:41]
        else : @[UART_tx.scala 61:20]
          clkCnterReg <= UInt<11>("h00") @[UART_tx.scala 62:21]
          node _bitCnterReg_T = add(bitCnterReg, UInt<1>("h01")) @[UART_tx.scala 63:36]
          node _bitCnterReg_T_1 = tail(_bitCnterReg_T, 1) @[UART_tx.scala 63:36]
          bitCnterReg <= _bitCnterReg_T_1 @[UART_tx.scala 63:21]
          node _outDataReg_T = dshr(inDataReg, bitCnterReg) @[UART_tx.scala 65:32]
          node _outDataReg_T_1 = bits(_outDataReg_T, 0, 0) @[UART_tx.scala 65:32]
          outDataReg <= _outDataReg_T_1 @[UART_tx.scala 65:20]
          stateReg <= UInt<2>("h02") @[UART_tx.scala 66:18]
          skip @[UART_tx.scala 61:20]
        skip @[Conditional.scala 39:67]
      else : @[Conditional.scala 39:67]
        node _T_4 = eq(UInt<2>("h02"), stateReg) @[Conditional.scala 37:30]
        when _T_4 : @[Conditional.scala 39:67]
          node _T_5 = lt(clkCnterReg, UInt<10>("h0364")) @[UART_tx.scala 70:25]
          when _T_5 : @[UART_tx.scala 70:41]
            node _clkCnterReg_T_2 = add(clkCnterReg, UInt<1>("h01")) @[UART_tx.scala 71:36]
            node _clkCnterReg_T_3 = tail(_clkCnterReg_T_2, 1) @[UART_tx.scala 71:36]
            clkCnterReg <= _clkCnterReg_T_3 @[UART_tx.scala 71:21]
            stateReg <= UInt<2>("h02") @[UART_tx.scala 72:18]
            skip @[UART_tx.scala 70:41]
          else : @[UART_tx.scala 73:20]
            clkCnterReg <= UInt<11>("h00") @[UART_tx.scala 74:21]
            node _T_6 = lt(bitCnterReg, UInt<4>("h08")) @[UART_tx.scala 75:27]
            when _T_6 : @[UART_tx.scala 75:44]
              node _outDataReg_T_2 = dshr(inDataReg, bitCnterReg) @[UART_tx.scala 77:34]
              node _outDataReg_T_3 = bits(_outDataReg_T_2, 0, 0) @[UART_tx.scala 77:34]
              outDataReg <= _outDataReg_T_3 @[UART_tx.scala 77:22]
              node _bitCnterReg_T_2 = add(bitCnterReg, UInt<1>("h01")) @[UART_tx.scala 78:38]
              node _bitCnterReg_T_3 = tail(_bitCnterReg_T_2, 1) @[UART_tx.scala 78:38]
              bitCnterReg <= _bitCnterReg_T_3 @[UART_tx.scala 78:23]
              stateReg <= UInt<2>("h02") @[UART_tx.scala 79:20]
              skip @[UART_tx.scala 75:44]
            else : @[UART_tx.scala 80:22]
              bitCnterReg <= UInt<4>("h00") @[UART_tx.scala 81:23]
              outDataReg <= UInt<1>("h01") @[UART_tx.scala 83:22]
              stateReg <= UInt<2>("h03") @[UART_tx.scala 84:20]
              skip @[UART_tx.scala 80:22]
            skip @[UART_tx.scala 73:20]
          skip @[Conditional.scala 39:67]
        else : @[Conditional.scala 39:67]
          node _T_7 = eq(UInt<2>("h03"), stateReg) @[Conditional.scala 37:30]
          when _T_7 : @[Conditional.scala 39:67]
            node _T_8 = lt(clkCnterReg, UInt<10>("h0364")) @[UART_tx.scala 89:25]
            when _T_8 : @[UART_tx.scala 89:41]
              node _clkCnterReg_T_4 = add(clkCnterReg, UInt<1>("h01")) @[UART_tx.scala 90:36]
              node _clkCnterReg_T_5 = tail(_clkCnterReg_T_4, 1) @[UART_tx.scala 90:36]
              clkCnterReg <= _clkCnterReg_T_5 @[UART_tx.scala 90:21]
              stateReg <= UInt<2>("h03") @[UART_tx.scala 91:18]
              skip @[UART_tx.scala 89:41]
            else : @[UART_tx.scala 92:20]
              clkCnterReg <= UInt<11>("h00") @[UART_tx.scala 93:21]
              outTxDoneReg <= UInt<1>("h01") @[UART_tx.scala 94:22]
              stateReg <= UInt<2>("h00") @[UART_tx.scala 95:18]
              skip @[UART_tx.scala 92:20]
            skip @[Conditional.scala 39:67]
    
  module UART_top : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip uart_rxd : UInt<1>, uart_txd : UInt<1>, led : UInt<8>}
    
    reg rx_done : UInt<1>, clock @[UART_top.scala 15:28]
    reg rx_data : UInt<8>, clock @[UART_top.scala 16:28]
    wire tx_busy : UInt<1> @[UART_top.scala 18:29]
    wire tx_done : UInt<1> @[UART_top.scala 19:29]
    inst M_uart_rx of UART_rx @[UART_top.scala 21:31]
    M_uart_rx.clock <= clock
    M_uart_rx.reset <= reset
    inst M_uart_tx of UART_tx @[UART_top.scala 22:31]
    M_uart_tx.clock <= clock
    M_uart_tx.reset <= reset
    io.led <= rx_data @[UART_top.scala 24:21]
    M_uart_rx.io.i_serial_data <= io.uart_rxd @[UART_top.scala 26:33]
    rx_done <= M_uart_rx.io.o_rx_done @[UART_top.scala 27:33]
    rx_data <= M_uart_rx.io.o_data @[UART_top.scala 28:33]
    M_uart_tx.io.i_tx_trig <= rx_done @[UART_top.scala 30:33]
    M_uart_tx.io.i_data <= rx_data @[UART_top.scala 31:33]
    tx_busy <= M_uart_tx.io.o_tx_busy @[UART_top.scala 32:33]
    tx_done <= M_uart_tx.io.o_tx_done @[UART_top.scala 33:33]
    io.uart_txd <= M_uart_tx.io.o_serial_data @[UART_top.scala 34:33]
    
